White paper by Stelios Androulidakis

Process Engineering Manager

SAE Circuits Colorado, Inc.

Rev b 5-7-13

There is a good reason behind every advancement  in Printed Circuit Technology which adds new requirements for fabricators. Blinds vias are a perfect example.

A via hole is a hole in the circuit board used only for making connections between layers, and not for components. A blind via is a plated via hole (usually smaller than 0.025”) that is only open to one side. It doesn’t go all the way through like all other holes do. (See Example below)


In order to build a blind and/or buried via board, the panel must be built sequentially, In other words, several sub-boards are fabricated first, then bonded together, making a final full board.


  • A layer with plated vias will process very similar to a regular cap construction job. Since they look similar, the two can be confused for each other. In many cases, a blind via job will have to have the other side as a cap construction, so this can get even more confusing.standard_4_layer
  • On a cap construction job, Layers next to the outside are imaged and plated up, then etched. (For example on a cap 4 layer, layers 1 and 2 will be together on a core, and layers 3 and 4 will be together. Layers 2 and 3 (the inside layers) will get imaged like an outer layer and plated with copper and tin, then resist stripped and Layers 1 and 4 become the outer layer, so they are protected all the way and must remain copper. This means that the panels have to come back in dry film to cover the back side before etching.)cap_constructioon_layers
  • When one side is a blind via layer, then it gets more complicated. Instead of just covering the back side with film before plating, pads are required for the via holes. Cuposit is first, so the holes can be metallized, after cuposit, in dry film, the same thing happens to the inside layer as in cap construction, but the outside now gets pads for the via holes. This is referred to as a “Button Plate” layer. This layer is very important to assure there are electrical connections to these via holes.plated_via_layers


If you need any clarification with this document, please contact Stelios Androulidakis, Process Engineering Manager (ext. 153).

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