Surface Topography of Copper in High Frequency RF applications

The irregularity of a machined, rolled, or electrodeposited metal surface is the result of the manufacturing process, including the choice of tools or deposition method,  machine geometry, and environmental conditions. When examined under high magnification, what seems to be a smooth surface can actually be quite irregular, with peaks and valleys. These peaks and valleys can be measured and used to define the condition and sometimes the performance of the surface. There are more than 100 ways to measure a surface and analyze the results, but the most common measurement of the surface texture is the roughness measurement. 

In North America, the most common parameter for surface texture is Average Roughness (Ra). Ra is calculated by an algorithm that measures the average length between the peaks and valleys and the deviation from the mean line on the entire surface within the sampling length. Ra averages all peaks and valleys of the roughness profile and then neutralizes the few outlying points so that the extreme points have no significant impact on the final results. 

In Europe, and in the electronic copper foils market, the more common parameter for roughness is Mean Roughness depth (Rz). Rz is calculated by measuring the vertical distance from the highest peak to the lowest valley within five sampling lengths, then averaging these distances. Rz averages only the five highest peaks and the five deepest valleys—therefore extremes have a much greater influence on the final value. Over the years the method of calculating Rz has changed, but the symbol Rz has not. As a result, there are three different Rz calculations still in use.

Depending on the manufacturing method of a given copper laminate, the foil can be graded depending on this Rz Mean Roughness depth value. Standard HTE foils can look quite rough under an SEM (Scanning electron microscope), as evidenced in the picture above. One can easily see how a signal can degrade as it travels over this uneven surface, or how a signal detection at 10Ghz or above can be missed.

The reason is the Skin Effect. The Skin Effect is the tendency of an alternating
current to become distributed within the conductor its traveling along, such that the current density is largest near the surface, and decreases with greater depths
in the conductor. The higher the frequency, the greater the tendency for current to take the path of low inductance on the outer surface of the conductor. The skin depth is given by the following formula below where the skin depth in microns is calculated.


δ = SQRT(2/(2(π) f µ σ)

f is the frequency in MHz, and as it increases, the skin depth (δ) decreases. By the time 15GHz is reached, the outermost portion of the conductor is utilized by the current, and as a result, the path becomes uneven and can result in increased resistance, as well as signal degradation and speed loss.

In order to accommodate this need, the circuit board and RF laminate industry has developed foils with finer grain sizes, allowing for unparalleled planarity at this level. Foils such as VLP, VLP-2, and VSP are all the buzzword in the RF materials arena. They also come with a hefty additional price tag, and must be specified. I know of quite a few design engineers trying to work in the 10-15GHz range who will order expensive Teflon based materials without assuring VLP foil is used.

Additionally, new foils have been developed with even smaller Rz for both higher RF frequencies, as well as higher speed signals for PCBs. HVLP and ULP coppers are available at a premium.

The easiest way to assure you will get the best quality foil without having to spell it out is to order material with thinner copper. Standard 2 oz., 1 oz., and 1/2 oz. copper clad materials and foils all have the same basic HTE topography, but 1/4 oz. and 3/8oz. copper foils and substrates do not. As a result of manufacturing a thinner foil, the bonus is automatically a smaller grain size and increased planarity at the micron level. If you are currently experimenting with different designs, you may want to consider these thinner foils. (This is not as good of an idea is you are expecting to require heat dissipation…)

What Surface Finish

What’s the best PCB Final Finish for my particular application?

White paper by Stelios Androulidakis

There has been much debate over the years as to what the best final finish is for a particular application. Gone are the days when 63/37 or 70/30 Sb/Pb were the norm. The standard solder finish has now been replaced by several Lead-Free HASL finishes, ENIG, ENEPIG, OSP, Immersion Silver, Immersion Tin, and even more obscure coatings such as Tin/Nickel and other exotic metals.

The main factors pushing for change and experimentation have been both price and dependability. As tin whiskers (otherwise known as tin migration) became the new dirty word in electronics, concern over inter-metallic layers and solder joint dependability only exasperated the production engineer’s worries.

From a board fabricator’s point of view, aside form the obvious price considerations, only a few of these coatings have held up over the years, and some have obvious advantages (and disadvantages).

The oldest and most dependable coating for through-hole technology is of course Tin/Lead solder. As surface mount technology decreased the pitch, this coating no longer had the planarity needed for efficient SMT component placement. Lead-free solder does have slightly better planarity, but this is mainly due to the higher temperatures at Hot Air Solder Leveling, rendering the liquid solder less viscous.

The advent of RoHS and ongoing bans on lead are making this surface coating obscure for most applications, except for military use.

Alternative surface coatings all have a better planarity, lending themselves to be more conducive to SMT design.

The most common alternative coating is ENIG (Electroless Nickel Immersion Gold). This is the most dependable over time, and remains solderable for years even after having undergone adverse conditions.  It is of course the most expensive per square inch. One of the most common misconceptions for ENIG gold is that “thicker is better”. The ideal thickness for ENIG is 2-3 microinches. A thicker coating of gold on ENIG can develop micro-cracks in the base nickel coating, so it is best to limit the thickness.

Price concerns have allowed for Immersion Silver, Immersion Tin, and OSP to also enter the scene, each with its own advantages and disadvantages. The main disadvantage of all three of the above coatings is their susceptibility to oxidation or external contamination.  Silver can oxidize under high humidity, exposure to chlorides, sulfates, or fingerprint oils. Tin and oxidize as well, unless properly stored. Silver or Tin coated boards must either be assembled in a timely manner or be stored in a controlled environment. Boards with these finishes cannot be safely re-baked if necessary. The same goes for OSP.

When wire-bonding becomes necessary, ENIG is no longer a good alternative. There are usually two options. A selective finish of ENIG, Silver, or Lead-Free HASL for the solderable surfaces and Hard Gold for the wire bonded surfaces is usually necessary, making for an expensive board. This is where ENEPIG (Electroless Nickel Electroless Palladium Immersion Gold) outshines them all. The use of ENEPIG avoids selective finish requirements for boards that require wire bonding & soldering on the same surface.

Development of new or improved older coating is ongoing. Originally, immersion silver coatings had issues with galvanization, but newer formulations have made this issue a thing of the past. Immersion Tin originally had problems with tin migration, but new additives are also eliminating this issue. New ENIG formulations now give even more planar coatings with increased solderability and dependability. As long as your fabricator’s coatings keep improving, your yields are guaranteed to go up. The new surface finishes have a bright, shiny future.




White paper by Stelios Androulidakis

SAE Circuits Colorado, Inc.

Rev b 1-16-15

In today’s digital electronics interference is a big concern, especially when it comes to video, usb interfaces, Ethernet, and other wireless communications. “Noise” in a circuit can result in anything from poor picture quality to a loss or degradation of critical signals.

Every wire and every circuit that transmits electricity has a resulting electromagnetic field around it, surrounding it and affecting the surrounding area. This can actually be felt by a human being near high power lines.  Though circuits on a board do not carry near as much electricity as a high power line, the electromagnetic field is still there, even though it’s a lot weaker. 

In a critical design, the electromagnetic field can interfere with the signal flow in an adjacent circuit (see illustration below). This field can be controlled by the width and height of the circuit, as well as its proximity to a plane layer.


Impedance is measured in Ohms.

A Signle-Ended impedance circuit is one circuit by itself, and the impedance reading concerns  the effect it is having on the surrounding circuitry. This circuit could still be in a group, but it is evaluated independently. A high impedance from a circuit in a sensitive area can interfere with surrounding signals. In the digital world, this can lead to excessive noise or other problems.


In order to have a circuit that will not affect surrounding signals, as a rule of thumb, the distance to the nearest adjacent circuit or feature of any kind must be 20X the circuit width. Since that is not possible in today’s high density designs, the impedance of a circuit can be controlled using a variety of different methods;  from specialty materials with varying Dk values, to varying the distance to a plane layer, which helps absorb excess electromagnetic radiation. Varying the circuit width and height will also have a major effect in the surrounding impedance.

Single –ended impedance can easily be controlled once a baseline is determined. Bringing a plane layer (power or ground) closer to the signal layer lowers the impedance, since more of it is absorbed by the surrounding metal. Similarly, the circuit can be surrounded by a ground plane on the same layer, in order to form what is known as a co-planar  waveguide, in order to achieve the same results. What matters is the distance to ground, and the “dielectric” of the layers the electromagnetic  waves must travel trough in order to get absorbed by the metal.

Since bringing the ground closer lowers the impedance, adding prepreg and increasing the distance to the ground layer will inversely increase the impedance.

Another factor is the total cross-sectional area of the circuit or wire. The height and the width are very critical. As the circuit’s cross-sectional area decreases, the impedance increases. Adversely, as the cross sectional area increases, the impedance decreases. (This is due to the reduced distance ratio to the plane layer, as the cross-sectional area is increased, as long as the power requirement stays the same.)

For example: If I have a circuit that is testing at 60 Ohms and I want it to be 50 Ohms, I can either increase the circuit width while maintaining the same dielectric distance, use heavier copper to increase the circuit height while still maintaining the same dielectric distance, or I can bring the ground plane closer by using a thinner core or less prepreg.

Differential impedance involves two circuits running parallel to each other, and the effect they have on each other’s signals. Even impedance is calculated when the signals are traveling  the same way, and odd impedance is calculated when the signals are running opposite from each other. The Differential is calculated using both the odd and even. Generally, differential impedance is used to match the circuits on a board to the cable it will connect.  For example:

USB cables are a standard twisted pair of wires with 90 Ohm differential impedance. Circuits designed to connect to that usb cable are generally required to be 100 Ohms ±10%; better than the required impedance of the cable. (This is mostly due to the price of cables vs the price of an assembled board.)

Another example is Ethernet, which uses cables of 100 Ohm impedance. The circuits designed to connect to this cable will  generally be 100 Ohms ±10%, while the ethernet cables are ±15%.


Other Uses:  Another reason to pay attention to impedance control becomes obvious when designing time delay circuits, and high speed transimission circuitry. In the case of time delay circuitry, the same 20X width rule of thumb applies, otherwise impedance from a circuit can affect the overall time delay capabilities or degrade the signal altogether.



Having one or two impedance requirements on a board is becoming relatively standard, depending on the connectivity required. This is becoming prevalent on more and more designs.  Each circuit will have an effect on the surrounding area, and with each impedance requirement, the margin of error increases. It is not uncommon for us here at SAE Circuits to build a 16 layer board with a single ended 50 Ohm controlled impedance on each signal layer along with 90 Ohm USB and 100 Ohm Ethernet circuits on those same layers. Needless to say, precision is the key to success. A need for speed can and will only hinder this demanding process.

Another major factor in the success of controlling the impedance of a circuit (or any conductor for that matter) is the size. The larger the circuit, the easier it is to control the impedance in a production environment.  It is relatively easy and repeatable  to control an etched circuit to ± 0.5 mil width. This is relatively easy to process in a production environment, and repeatability is 100% when your board is designed to have 12 mil circuits. When the circuitry is reduced to 4 mils or less, though, controlling the circuit width to ± 0.5 mil is no longer acceptable. This is due to the fact that the requirement is in a % ratio. (0.5 mil is 12.5% of a 4 mil circuit, when it is only 4.2% of a 12 mil circuit.)

This thinner the circuitry the more demanding the manufacturing process. Tolerances can drop below the point where it is no longer physically possible to control the width of a circuit. If the required circuitry gets small enough, the edge of the circuit itself becomes a factor.

Examples are shown below:

Circuit Width & space of 100 Ohm Differential Pair

Controlled to ± 0.001” Standard Imaging/Etching

Controlled to ± 0.0005” VFL Process

Controlled to ± 0.00025” VFL Process with LDI


±8.3% of circuit width 0.011”-0.013”             95-105 Ohms            (±5% deviation)

±4.2% of circuit width   0.0115” – 0.0125”    97.5-102.5 Ohms (±2.5% deviation)

±2.1% of circuit width   0.001175”-9.001225”   98.75-101.25 Ohms (±1.25% deviation)


±14.3% of circuit width   0.006”-0.008”             91-109 Ohms           (±9% deviation)

±7.2% of circuit width   0.0065”-0.0075”     95.5-104.5 Ohms     (±4.5% deviation)

±3.6% of circuit width   0.00675”-0.00725”     97.75-102.25 Ohms   (±2.5% deviation)


25% of circuit width   0.003”-0.005”             84-116 Ohms         (±16% deviation)

12.5% of circuit width   0.0035”-0.0045”          92-108 Ohms            (±8% deviation)

6.3% of circuit width   0.00375”-0.00425”     96-104 Ohms            (±4% deviation)


As shown by the previous chart,  it is advantageous to design a 7 mil controlled impedance circuit over  a 4 mil for repeatability and manufacturability. Tolerances can become unbearable and unmanufacturable as circuitry is miniaturized.  Though there is a small amount of gained real estate, the resulting additional processing required to meet a ±10% differential impedance specification at this circuit width will become cost prohibitive.

Etching using standard methods is usually controlled to within ½ mil on ½ oz copper. This effect can be cumulative between imaging and etching, so tight controls and measurements after all processing steps are key to achieving a successfull controlled impedance design in a finished product.

For any questions, suggestions, or clarifications regarding this document, feel free to contact:                      Stelios Androulidakis, Process Engineering,  SAE Circuits Colorado, Inc. at (303) 530-1900 ext 153 or 109 or stelios@saecircuits.com.


White paper by Steve Hodge

and Stelios Androulidakis

SAE Circuits Colorado, Inc.



Depending on details such as layer count and material types, boards can vary in cost greatly. In most cases, size and layer count dictate most of the board’s cost, yet there are a few little things that can be done to help lower the overall cost of fabrication, thereby reducing the price on a customer’s end.

The following chart shows two columns: the first is SAE Circuits standard capabilities, but the second column shows design details that can help increase the manufacturability. This helps drop the overall price.



Lower Cost

Max. Board Thickness



Max Number of Layers



Smallest Drilled Via Hole



Maximum Hole-to-Board Thickness Aspect Ratio

10 to 1

4 to 1

Cu Thickness Range

0.25 oz to 4 oz

1/2 oz

Best Panel Array Size(s)

8.25″ x 11.25″

No Array

Blind / Buried Vias



Controlled Depth or Selective Routing



Countersink Capability

All sizes, ±0.005″


Plugged Vias






Plated Slots



Ceramic, or Teflon Substrates



  • BOARD SIZE: Though all of the above-suggested changes can help lower the board price, one of the most important factors is size. We manufacture most products on 18”X24” production panels, so size of the board is directly proportional to price due to material costs. For multilayer boards, the usable area on this panel is 16.5”X22.5”. The more boards we can fit on this panel, the better.
  • LAYER COUNT and THICKNESS: Many designers are used to designing boards with the standard thickness of 0.062”. This has been a standard thickness ever since the late 1960s when 1/16” counter laminate was used to make the first circuit boards. This is not a standard based on material resistance or anything that important. As a matter of fact, today’s pre-pregs have such good resistance, that a mere 0.003” will keep a 400V arc at bay. If you are willing to move away from the “standard thickess” models, you will find that you can easily shave up to 20-30% of the bare board price for a standard 4 or 6 layer board. For a double sided board, try a 0.047” or 0.039” thickness, and you’ll be amazed at how much your board price can drop.

There are different approaches that can be used when looking to save money and resources on a specific design. Please don’t hesitate to contact us at stelios@saecircuits.com with your individual need.


White paper by Steve Hodge

and Stelios Androulidakis

SAE Circuits Colorado, Inc.

When quoting a printed circuit board, there is certain information needed for accuracy. We appreciate opportunities and will do our best to get things right. We custom manufacture boards and RF antennas, and we see a very wide range of requirements and intricacies in new designs. More detailed information is always better than a lack of information. (Blow up diagrams in a print, detailing special areas that require attention, are ideal.)

Some requests do not include all the information needed to perform a valid quote the first time. Below are some suggestions:

  • The very least needed for an accurate quote: Gerber files with an NC drill file included.
  • RoHS or Non-RoHS? Also include the desired pad finish. i.e. ENIG, Immersion Silver, lead free HASL etc.
  • Do you want your boards in an array or single? If in an array, do you prefer rout and retain separation, or scoring?
  • Fab notes that include desired copper weight , solder mask color, silk screen color and overall thickness.
  • Are there any other special requirements? (Special materials, peelable soldermask, controlled impedance circuitry (do you want impedance tested), etc.)

For the best possible accuracy, it is best to:

  • have a complete drawing with fab notes
  • nice to have an array drawing if matching an existing stencil or components over the edge
  • It also is important to include the required volume and delivery.


In short, it is best to leave out all the speculation on our end. Tell us what you really want and we will respond more quickly and accurately. Parts that come in for quote lacking this information will be quoted using SAE Circuits Colorado’s “Default Manufacturing Specifications”, which can be found on our webpage at www.saecircuits.com under Technical Resources.





White paper by Stelios Androulidakis

Process Engineering Manager

SAE Circuits Colorado, Inc.

Rev b 5-7-13

There is a good reason behind every advancement  in Printed Circuit Technology which adds new requirements for fabricators. Blinds vias are a perfect example.

A via hole is a hole in the circuit board used only for making connections between layers, and not for components. A blind via is a plated via hole (usually smaller than 0.025”) that is only open to one side. It doesn’t go all the way through like all other holes do. (See Example below)


In order to build a blind and/or buried via board, the panel must be built sequentially, In other words, several sub-boards are fabricated first, then bonded together, making a final full board.


  • A layer with plated vias will process very similar to a regular cap construction job. Since they look similar, the two can be confused for each other. In many cases, a blind via job will have to have the other side as a cap construction, so this can get even more confusing.standard_4_layer
  • On a cap construction job, Layers next to the outside are imaged and plated up, then etched. (For example on a cap 4 layer, layers 1 and 2 will be together on a core, and layers 3 and 4 will be together. Layers 2 and 3 (the inside layers) will get imaged like an outer layer and plated with copper and tin, then resist stripped and Layers 1 and 4 become the outer layer, so they are protected all the way and must remain copper. This means that the panels have to come back in dry film to cover the back side before etching.)cap_constructioon_layers
  • When one side is a blind via layer, then it gets more complicated. Instead of just covering the back side with film before plating, pads are required for the via holes. Cuposit is first, so the holes can be metallized, after cuposit, in dry film, the same thing happens to the inside layer as in cap construction, but the outside now gets pads for the via holes. This is referred to as a “Button Plate” layer. This layer is very important to assure there are electrical connections to these via holes.plated_via_layers


If you need any clarification with this document, please contact Stelios Androulidakis, Process Engineering Manager (ext. 153).



White paper by Stelios Androulidakis

Process Engineering Manager

SAE Circuits Colorado, Inc.

Rev A 4-10-13

In today’s electronics manufacturing climate higher densities and hotter components on the boards require more heat dissipation than ever before. To date, the standard method has been to add heat-sinks where the heat dissipation is needed most.


Heat-sinks can be cumbersome and pricey, and they take up a lot of real estate.  Furthermore, the added volume can keep boards from sliding into tight spaces where they may be needed.

The newer High Intensity LED technology is more demanding of heat dissipation than previous technologies so far, and heat sinks are too bulky and block too much LED light to be of any use. As a result, a new aluminum substrate was born with incredible heat dissipative properties .


Since the substrate itself is the heat sink, heat generation becomes a worry of the past. There are of course some limitations. Due to the fact that only one side of the board can be used for circuitry, there are limits in design. This technology lends itself well to surface mount assembly, but not so much on the older through-hole designs.


Here at SAE Circuits we have developed the ability to custom fabricate your design using this aluminum substrate. Aluminum thickness, dielectric thickness, and copper weights can all be customized to your distinct specifications.

Please feel free to contact SAE Circuits Colorado, Inc. at 303-530-1900 for further details.